HDI PCB Stackup Guide, Selector & Cost Calculator

HDI stackup types

HDI stackups are named by build-up layers per side, then core layers: 1+N+1, 2+N+2, 3+N+3, and any-layer. Each extra build-up layer adds a press cycle and a microvia level, reaches a finer BGA pitch, and costs more.

Presses in brackets: on a single two-layer core. µvia levels are per side. Cost is relative to a through-hole board of the same size, layer count (8–10) and quantity. Values are typical, not limits.
Build	IPC type	Presses	µvia levels	Finest pitch	Cost	Typical products
Through-hole	—	1	0	0.8 mm	1.0×	Industrial, power, general digital
1+N+1	I or II	2 (1)	1	0.5–0.65 mm	1.3–1.5×	IoT modules, cameras, automotive ECUs
2+N+2	III	3 (2)	2	0.4–0.5 mm	1.7–2.3×	SoMs, FPGA and SoC boards, tablets
3+N+3	III	4	3	0.35–0.4 mm	2.4–2.9×	Handhelds, dense processor modules
Any-layer (ELIC)	III	4 (10 layers)	All	0.35 mm and below	3.0–4.0×	Smartphones, wearables

What “1+6+1” tells the fabricator

The numbers describe how the board is pressed, not only how many layers it has. In 1+6+1, a six-layer core is laminated and drilled first, then one layer of laser-drillable dielectric and copper is pressed onto each side. In 2+4+2 that build-up step happens twice.

Each build-up cycle means another press, another laser-drill and plating pass, and another registration step. That is why cost and lead time follow the first digit rather than the total layer count.

PCBSync, the fabricator we work with, covers microvia sizes, sequential lamination and the more advanced any-layer and coreless builds in its HDI PCB design and manufacturing guide.

Three lamination steps of an 8-layer 2+4+2 HDI board — **Figure 5.** An 8-layer 2+4+2 takes three presses: the core first, then one per build-up layer.

Standard 8-layer PCB stackup with through vias only — **Figure 6.** The baseline: an 8-layer board pressed once, every via drilled through all layers.

The starting point: through vias only

Every HDI build starts from a board like this. The difference is where the vias stop. A through via takes space on all eight layers even if it only joins two; a microvia takes space only on the two layers it joins.

IPC-2226 Types I, II and III

IPC-2226 groups HDI builds by via structure. Type I has one microvia layer per side with through vias only. Type II adds buried vias in the core. Type III has two or more microvia layers on at least one side, which covers 2+N+2, 3+N+3 and any-layer boards.

Cross-sections of IPC-2226 HDI Type I, Type II and Type III — **Figure 7.** IPC-2226 Types I to III. Type II is the most common 1+N+1 build, because buried vias free the core for routing.

1+N+1: one build-up layer per side

One laser-drilled layer on each side of an N-layer core. Microvias link L1 to L2; buried vias cross the core. It takes two presses (one on a single two-layer core), costs about 1.3–1.5 times a through-hole board, and gives two escape layers inside a BGA footprint.

At 0.65 mm pitch and above, a buried via fits between the target pads on L2, so a 1+N+1 can escape any number of rows. At 0.5 mm it does not, and 1+N+1 works only when about two escape layers are enough. The 8-layer 1+6+1 in the viewer at the top of the page is the most common version.

4-layer 1+2+1 HDI stackup cross-section — **Figure 8.** A 4-layer 1+2+1: the smallest HDI build, pressed once.

6-layer 1+4+1 HDI stackup cross-section — **Figure 9.** A 6-layer 1+4+1 on a four-layer core.

Example stackup: 8-layer 1+6+1, about 1.0 mm

Total ≈ 1.04 mm over copper, before solder mask. Pressed prepreg thickness varies with copper density.
Layer	Material	Thickness (µm)	Use
L1	Copper, 12 µm foil + plating	30	Components, BGA escape
	Build-up prepreg 1080 / 1086	70	L1–L2 microvias
L2	Copper, plated	30	Ground, microvia landing
	Core	150
L3	Copper, ½ oz	18	Signal (stripline)
	Prepreg 2116	110
L4	Copper, 1 oz	35	Power
	Core	150
L5	Copper, 1 oz	35	Ground
	Prepreg 2116	110
L6	Copper, ½ oz	18	Signal (stripline)
	Core	150
L7	Copper, plated	30	Ground, microvia landing
	Build-up prepreg 1080 / 1086	70	L8–L7 microvias
L8	Copper, 12 µm foil + plating	30	Components

Give each span its own drill file.
Span	Via type	Typical size	Notes
L1–L2, L8–L7	Laser microvia	0.10 mm hole, 0.25 mm pad	Copper-filled when placed in a pad
L2–L7	Mechanical buried via	0.20 mm drill, 0.40–0.45 mm pad	Resin-filled before the build-up press
L1–L8	Mechanical through via	0.20–0.25 mm drill	Optional; filled and capped if in a pad

2+N+2: two build-up layers per side

Two build-up layers per side give three escape layers inside a BGA footprint, which is what most 0.4–0.5 mm processors need. Three presses (two on a single core); about 1.7–2.3 times a through-hole board.

Microvias can be stacked, where each lower via is copper-filled and planarised so the next one lands on flat copper, or staggered, offset by about a pad so no fill is needed. Stacking costs 10–15% more and saves area inside tight footprints; staggering is cheaper and holds up better in thermal cycling. Most boards mix both.

6-layer 2+2+2 HDI stackup cross-section — **Figure 10.** A 6-layer 2+2+2 on a single core: two presses, popular for thin modules.

10-layer 2+6+2 HDI stackup with staggered microvias — **Figure 11.** A 10-layer 2+6+2 with staggered microvias, for boards that need more planes.

Example stackup: 8-layer 2+4+2, about 1.05 mm

Total ≈ 1.05 mm over copper, before solder mask.
Layer	Material	Thickness (µm)	Use
L1	Copper, 12 µm foil + plating	30	Components, BGA escape
	Build-up prepreg 1080	70	L1–L2 microvias
L2	Copper, plated	30	Ground
	Build-up prepreg 1080	70	L2–L3 microvias
L3	Copper, plated	30	Signal
	Core	200
L4	Copper, 1 oz	35	Power
	Prepreg 2116	120
L5	Copper, 1 oz	35	Ground
	Core	200
L6	Copper, plated	30	Signal
	Build-up prepreg 1080	70	L7–L6 microvias
L7	Copper, plated	30	Ground
	Build-up prepreg 1080	70	L8–L7 microvias
L8	Copper, 12 µm foil + plating	30	Components

3+N+3: three build-up layers per side

For 0.35–0.4 mm BGAs that need four escape layers, or two dense BGAs back to back. Four presses; about 2.4–2.9 times a through-hole board. It keeps a drilled core with cheap buried vias, so it is a common halfway house before any-layer.

A three-high stack of copper-filled microvias is the structure most sensitive to thermal cycling. For Class 3, automotive or wide temperature ranges, stagger at least one level. Before choosing 3+N+3, check whether 2/2 mil lines on a 2+N+2 would remove the third build-up.

8-layer 3+2+3 HDI stackup cross-section — **Figure 12.** An 8-layer 3+2+3 on a single core: close to any-layer in routing freedom.

Example stackup: 10-layer 3+4+3, about 1.1 mm

Total ≈ 1.10 mm over copper, before solder mask.
Layer	Material	Thickness (µm)	Use
L1	Copper, foil + plating	30	Components, BGA escape
	Build-up prepreg 1067 / 1080	65
L2	Copper, plated	25	Signal
	Build-up prepreg 1067 / 1080	65
L3	Copper, plated	25	Ground
	Build-up prepreg 1067 / 1080	65
L4	Copper, plated	30	Signal
	Core	150
L5	Copper, 1 oz	35	Power
	Prepreg 2116	120
L6	Copper, 1 oz	35	Ground
	Core	150
L7	Copper, plated	30	Signal
	Build-up prepreg 1067 / 1080	65
L8	Copper, plated	25	Ground
	Build-up prepreg 1067 / 1080	65
L9	Copper, plated	25	Signal
	Build-up prepreg 1067 / 1080	65
L10	Copper, foil + plating	30	Components

Any-layer (ELIC): every layer is a build-up layer

An any-layer board starts from a thin laser-drilled core and adds build-up layers one pair at a time, each with copper-filled microvias. There are no drilled vias, so any layer can connect to any other. It is usually paired with mSAP, which plates traces up to about 30/30 µm lines and spaces.

It suits phones, watches and earbuds, with packages at 0.35 mm pitch and below. It costs 3–4 times a through-hole board and takes four to five weeks, so a 3+N+3 or a 2+N+2 with finer lines is often close enough for industrial products.

8-layer any-layer ELIC HDI stackup cross-section — **Figure 13.** An 8-layer any-layer build: three build-up presses around a thin core.

Example stackup: 10-layer any-layer, about 0.7 mm

Total ≈ 0.71 mm over copper for a 10-layer ELIC board.
Element	Material	Thickness	Notes
L1, L10	Copper, foil + plating	25 µm	Outer layers, finished
L2–L9	Copper, plated	18 µm each	Every layer carries filled microvias
8 build-up layers	Build-up prepreg 1037 / 1067	55 µm each	Laser-drillable, spread glass
L5–L6	Thin core	75 µm	Laser-drilled and copper-filled first

How to choose a build

Find the finest-pitch BGA and count the signal rows that must escape.
Work out how many tracks fit between its pads; each layer escapes that many rows plus one.
At 0.65 mm pitch and above, 1+N+1 covers any depth. Below that, add one build-up layer for each escape layer beyond L1.
Add reference planes, then decide stacked or staggered microvias and the laminate.

The stackup selector below does the arithmetic. Every thickness here is a starting point: pressed dielectric depends on resin content and on the copper it flows into, so ask for a stack drawing with calculated impedance before you route. PCBSync's HDI PCB Stackup guide explains how it plans, presses and verifies these builds at the factory.

Stackup selector

Enter the finest BGA pitch, the balls per side and your line width. The selector works out how many microvia levels you need and suggests the smallest build that routes it.

Suggested minimum build

2+2+2, 6 layers

0.5 mm pitch with 0.25 mm pads leaves 250 µm between pads: one track fits at 3/3 mil.
Each routing layer escapes about 2 rows; 8 rows deep with 30% power/ground leaves about 6 signal rows, so 3 escape layers.
At this pitch drilled vias do not fit inside the array, so every escape layer must be reached by microvias: that takes 2 build-up layers per side.
This is the minimum count, with a reference plane for each escape layer. Extra planes and power go in the core, so 2+4+2 (8 layers) is the usual next step up.
Stacked, copper-filled microvias save space; staggered ones cost less and are more robust.

BGA fanout by pitch

Everything in BGA escape routing follows from one number: how many tracks fit between two neighbouring pads. With track width equal to space, as it usually is:

tracks = floor( (pitch − pad − w) ÷ 2w )

Number of 75 micron tracks that fit between BGA pads at 0.8, 0.65, 0.5 and 0.4 mm pitch — **Figure 14.** At 75/75 µm lines, 0.8 mm pitch fits two tracks, 0.65 and 0.5 mm fit one, and 0.4 mm fits none.

Tracks that fit between two adjacent pads at each line width. Rows escaped per layer is this number plus one.
Pitch	Pad (NSMD)	Gap	4/4 mil lines	3/3 mil lines	2/2 mil lines
1.0 mm	0.50 mm	500 µm	2	2	4
0.8 mm	0.40 mm	400 µm	1	2	3
0.65 mm	0.30 mm	350 µm	1	1	3
0.5 mm	0.25 mm	250 µm	0	1	2
0.4 mm	0.23 mm	170 µm	0	0	1
0.35 mm	0.20 mm	150 µm	0	0	1

From tracks to escape layers

On each layer the outer row routes straight out and every track between pads carries one more row, so a layer escapes tracks + 1 rows. Signal rows divided by that, rounded up, is the number of escape layers.

Signal rows are fewer than physical rows because power and ground balls usually sit in the centre and go straight down to planes. Count from the ball map, not the ball count.

At 0.65 mm pitch and above a drilled buried via fits between the L2 pads, so 1+N+1 reaches any inner layer. At 0.5 mm and below each escape layer beyond L1 needs its own microvia level: two escape layers is 1+N+1, three is 2+N+2, four is 3+N+3.

Which layer each row of a 0.5 mm pitch BGA escapes on — **Figure 15.** At 0.5 mm pitch with one track between pads, each layer takes two rows.

Worked examples

Signal rows assume 25–30% of balls are power and ground in the centre. Same method as the stackup selector.
BGA	Lines	Rows / layer	Signal rows	Escape layers	Minimum build
0.8 mm, 23 × 23	4/4 mil	2	9	5	10-layer, through vias (no HDI)
0.65 mm, 20 × 20	3/3 mil	2	8	4	1+6+1, 8 layers
0.5 mm, 16 × 16	3/3 mil	2	6	3	2+2+2, 6 layers
0.4 mm, 14 × 14	3/3 mil	1	5	5	Any-layer (ELIC), 10 layers
0.4 mm, 14 × 14	2/2 mil	2	5	3	2+2+2, 6 layers

The last two rows are the same package. Moving from 3/3 to 2/2 mil lines lets one track through the 0.4 mm gap, doubles the rows per layer and drops two build-up layers, which is usually cheaper than the extra presses.

Dog-bone fanout at 0.8 mm pitch compared with via-in-pad at 0.4 mm pitch — **Figure 16.** Same scale. At 0.8 mm a drilled via fits on the diagonal; at 0.4 mm only a via in the pad will fit.

Dog-bone or via-in-pad

A dog-bone runs a short track from each pad to a drilled via on the diagonal between four pads. It works down to 0.8 mm pitch with 0.2 mm drills, and at 0.65 mm with small drills and tight pads. Below that the via has to go in the ball pad itself, copper-filled and plated flat.

Habits that save a layer

Fan out the whole BGA before routing anything else.
Keep L2 as ground with landing pads; avoid long slots cut by routing.
Route the outer two rows on L1, with no via at all.
Put decoupling capacitors under the BGA on the back, each with its own via-in-pad.
Check differential pairs early: a 100 Ω pair rarely fits between 0.5 mm pads.

Microvia design

A microvia is a laser-drilled blind via through one thin dielectric, with an aspect ratio of no more than 1:1. Start from a 0.10 mm hole with 0.25 mm pads through 60–80 µm of dielectric, keep the aspect ratio at 0.75:1 or lower, and copper-fill any microvia that is stacked or sits in a pad.

Laser microvia cross-section with capture pad, target pad, depth and aspect ratio — **Figure 17.** Aspect ratio is dielectric depth divided by the hole diameter at the top.

Anatomy and aspect ratio

The pad on the drilled side is the capture pad; the pad it lands on is the target pad, which also stops the CO₂ laser. Because the hole goes through only 40–100 µm of dielectric it can be far smaller than a mechanical drill, and that is where HDI density comes from.

A 0.10 mm hole through 70 µm of prepreg is 0.7:1 and plates reliably. Through 110 µm it is 1.1:1, over the limit. The depth that counts is the pressed thickness, which is thinner over sparse copper than over a plane.

Standard sizes

Typical fabrication values. The stack drawing from your fabricator overrides them.
Feature	Standard HDI	Advanced HDI	Notes
Laser hole, top	0.10 mm (4 mil)	0.075 mm (3 mil)	CO₂ laser through the dielectric
Laser hole, bottom	0.06–0.08 mm	0.05–0.06 mm	Laser holes taper; the bottom is 60–80% of the top
Capture pad (top land)	0.25 mm	0.20 mm	Hole + 0.15 mm; a little larger on the outer build-up of 3+N+3
Target pad (bottom land)	0.25–0.30 mm	0.20–0.25 mm	Solid copper, never a void in a plane
Dielectric depth	60–100 µm	40–60 µm	Pressed thickness of one build-up layer
Aspect ratio, depth : hole	0.75 : 1 or lower	up to 1 : 1	IPC-T-50 caps a microvia at 1 : 1
Stagger offset, centre to centre	0.25 mm or more	0.20 mm or more	The upper via must land on flat copper
Copper in the via	12 µm average minimum	12 µm average minimum	IPC-6012 Class 2 and 3
Fill	Resin from the next press	Copper-filled and planarised	Copper fill is required to stack or to sit in a pad

Stacked or staggered

Stacked microvias sit directly on each other; every lower level must be copper-filled and planarised. Staggered microvias are offset by about a pad diameter, so each lands on plain copper and no fill is needed. Stack where area is really short, inside a 0.4 mm BGA; stagger everywhere else.

A skip via goes from L1 straight to L3 through two dielectrics. It saves a pad but doubles the depth, so the hole must be larger. Check that your fabricator builds it first.

Via-in-pad

A microvia in a BGA pad must be copper-filled and plated flat, or solder paste flows into the hole and leaves a void. A good fill leaves a dimple of no more than about 15 µm. Mechanical vias in pads are resin-filled and copper-capped, IPC-4761 Type VII, often called VIPPO, and add roughly 10–15% to the board price.

Stacked copper-filled microvias compared with staggered microvias — **Figure 18.** A stacked column uses one pad of area but needs copper fill on every level below the top.

Reliability

The weak point of a microvia is the bond to the target pad. Resin expands in Z much more than copper, and the interface can crack during reflow. IPC documented this in its white paper IPC-WP-023: boards pass bare-board electrical test, then go open after assembly or in the field, and can reconnect when cool. Stacked filled microvias carry the most risk. For long-life, automotive or Class 3 products:

Stagger at least one level, or keep stacks to two levels.
Use a laminate with low Z-axis expansion and Td of 340 °C or more.
Keep the aspect ratio at 0.75:1 or lower, with a target pad of at least hole + 0.15 mm.
Ask for reflow-simulation coupons on the first lot, to IPC-TM-650 method 2.6.27.

How to design an HDI PCB

On a through-hole board you can route first and settle the stackup later. On HDI the stackup decides which vias exist, so it comes first.

Eight-step HDI PCB design workflow — **Figure 19.** The first four steps fix the stackup. Changing it after fanout usually means redoing most of the routing.

Find the part that sets the build. Usually the finest-pitch BGA. Get the ball map, not only the ball count.
Count escape layers from tracks between pads and signal rows, as in BGA fanout.
Choose the build type. At 0.8 mm and above you may not need HDI. At 0.65 mm, 1+N+1 escapes any depth. Below that: two escape layers 1+N+1, three 2+N+2, four 3+N+3, more any-layer.
Get a stack drawing from the fabricator with pressed dielectrics and impedance widths.

Set up via rules in CAD. Each span is its own via type: L1–L2 microvia, L2–L7 buried, L1–L8 through.
Fan out, then route. BGA microvias and escape tracks first, L2 kept as ground, then high-speed nets.
Write the fabrication notes. One drill file per span, a via table with fill types, IPC-6012 class, finish and impedance table.
Get a DFM review before release. Changes go back into the stack drawing first, then the routing.

Design rules at a glance

Typical values across HDI fabricators in 2026. Standard values are quoted by most shops; advanced values by fewer, at higher cost.
Parameter	Standard HDI	Advanced HDI	Notes
Line / space, outer layers	75 / 75 µm (3/3 mil)	50 / 50 µm (2/2 mil); 30 / 30 µm with mSAP	Measured on finished copper
Line / space, inner layers	75 / 75 µm	50 / 50 µm	Thinner copper etches finer
Laser microvia hole	0.10 mm	0.075 mm	Top diameter
Microvia pads, capture / target	0.25 / 0.25–0.30 mm	0.20 / 0.20–0.25 mm	See the microvia table
Build-up dielectric	60–100 µm	40–60 µm	Pressed thickness
Microvia aspect ratio	0.75 : 1	1 : 1	Depth to top diameter
Stacked microvia levels	2	3 or more, any-layer	Copper-filled
Mechanical drill, buried or through	0.20 mm	0.15 mm	Finished hole about 0.05 mm smaller
Mechanical via pad	Drill + 0.20 mm	Drill + 0.15 mm	Larger on thick cores
Through-hole aspect ratio	10 : 1	12 : 1	Board thickness to drill
Via-in-pad	Resin fill + copper cap, IPC-4761 Type VII	Copper-filled microvia	Planar to about 15 µm
Solder mask dam between pads	75 µm	50 µm with LDI	Below this, use a gang opening
Impedance tolerance	±10%	±7%	Some shops hold ±5% on request
Surface finish for fine-pitch BGA	ENIG	ENEPIG	Flat finishes; OSP for cost-sensitive builds

Impedance on thin dielectrics

Build-up dielectrics are two to three times thinner than standard prepregs, so a 50 Ω microstrip over 70 µm is only about 0.10 mm wide. Etch tolerance becomes a bigger share of the width, so take widths from the fabricator's stack drawing, not a generic calculator.

Materials

Build-up layers need laser-drillable spread-glass prepregs such as 1067, 1078 or 1086, or resin-coated copper. Every build-up is another press cycle, so look for Tg of 170 °C or more, Td of 340 °C or more and low Z-axis expansion.

Data package for a quote

Gerber X2 or ODB++, one drill file per via span named by layer pair, a stack drawing with the impedance table, a via table with fill types, and notes for IPC class, finish, thickness and panel.

HDI PCB cost calculator

HDI price follows the number of lamination cycles. At production quantities, for the same size, 1+N+1 typically costs 1.3–1.5 times a through-hole board, 2+N+2 about 1.7–2.3 times, 3+N+3 2.4–2.9 times and any-layer 3–4 times.

Budget range for the order

$498 – $864

$4.98 – $8.64 per board, 100 pcs

Build: 1+6+1, 8 layers
Press cycles: 2
Typical lead time: 10–15 working days
Cost index: 1.59× the same board with through vias only

What is adding to the price

HDI structure+40%
Material0%
Line width+8%
Filled via-in-pad+12%
Surface finish0%
Small quantity+35%
Lead time0%

Get an exact quote at PCBSync Send these specs on WhatsApp

Budget estimate only. Prices vary with panel use, copper weight, drill count, testing and material prices.

Relative bare-board cost of HDI structures compared with a through-hole board — **Figure 20.** Relative bare-board cost by build, same size, quantity and material.

Ways to bring the price down

Check whether finer lines remove a build-up layer. 2/2 mil costs less than a third press cycle.
Stagger microvias wherever there is room; stack only inside the tightest footprints.
Keep the build symmetric. Asymmetric builds bow and yield worse.
Use via-in-pad only where the fanout needs it.
Agree the panel size with the fabricator before fixing the outline.

How the estimate is calculated

The calculator multiplies board area (plus 15% for panel waste) by a base price per square centimetre for a through-hole board of that layer count, then applies a factor for each choice: build type, laminate, line width, via-in-pad, finish, quantity and lead time. A one-off engineering and tooling charge is added, scaled by the build. The range runs from 25% below to 30% above the central figure, because real quotes vary that much between shops and months.

The cost index includes the one-off charges, so at prototype quantities it sits above the production ranges quoted on this page. At a thousand pieces or more it settles close to them.

Common questions

What is an HDI PCB stackup?

An HDI (high-density interconnect) stackup is a layer build that adds thin, laser-drilled build-up layers on top of a conventionally laminated core. It is written as build-up layers per side + core layers + build-up layers, for example 1+6+1 or 2+4+2, and each build-up layer adds one lamination cycle.

Which HDI stackup do I need for a 0.5 mm pitch BGA?

A 0.5 mm BGA whose signals escape on two layers routes on a 1+N+1 build with via-in-pad microvias to L2. Deeper arrays usually need 2+N+2, because drilled buried vias do not fit between 0.5 mm pads, so every extra escape layer has to be reached with another microvia level.

Is 2+N+2 always better than 1+N+1?

No. It adds a press cycle and typically 30–50% to the bare-board price. Use it when BGA escape or routing density actually needs a second microvia level; otherwise a 1+N+1 with more core layers is cheaper and faster to build.

How much more does an HDI PCB cost than a standard multilayer?

For the same size, layer count and quantity, a 1+N+1 board typically quotes at 1.3–1.5 times a through-hole multilayer, 2+N+2 at about 1.7–2.3 times and any-layer at 3–4 times. HDI can still lower total cost when it removes layers or shrinks the board.

Can I put microvias in BGA pads on a 1+N+1 board?

Yes. Via-in-pad microvias are the main reason to use 1+N+1. Ask for copper-filled, planarised microvias so the pad stays flat for solder paste.

Do stacked microvias need copper filling?

Yes. Each lower microvia in a stack must be copper-filled and planarised so the next laser via lands on flat copper. Staggered microvias do not need this.

What does ELIC stand for?

Every Layer Interconnect. It is another name for any-layer HDI, where every layer pair is joined by laser microvias and any layer can connect to any other through stacked filled vias.

What is the maximum aspect ratio for a microvia?

IPC-T-50 defines a microvia as a blind structure with an aspect ratio of no more than 1:1 and a depth of no more than 0.25 mm. Most fabricators prefer 0.75:1 or lower, for example a 0.10 mm hole through a 70 µm dielectric.

Is via-in-pad required for a 0.4 mm BGA?

In practice, yes. The gap between 0.4 mm pitch pads is about 0.17 mm, too small for a drilled via or even a laser via pad beside the ball, so inner rows escape through copper-filled microvias in the pads.

What trace width is used on HDI boards?

Standard HDI uses 75/75 µm (3/3 mil) line and space. Advanced HDI goes to 50/50 µm (2/2 mil), and substrate-like PCBs built with mSAP reach about 30/30 µm. Impedance-controlled traces on thin build-up dielectrics are often close to 0.10 mm wide.

Which surface finish is best for HDI?

ENIG is the usual choice because it is flat, which matters for fine-pitch BGAs and via-in-pad. ENEPIG is used when there is wire bonding or a need for extra solder-joint robustness. OSP is flat and cheap but has a shorter shelf life. HASL is not suitable for fine pitch.

Can HDI make a board cheaper overall?

Yes, when it removes layers or shrinks the outline. A 0.5 mm BGA that would need 10 through-hole layers may route on 8 layers of 1+N+1, and a smaller board fits more times on a production panel, which lowers the unit price.

What files does a fabricator need to quote an HDI board?

Gerber or ODB++ data, one drill file per via span (for example L1–L2, L2–L7 and L1–L8), a stackup drawing with materials and dielectric thicknesses, the impedance table, and fabrication notes covering via fill, IPC class and surface finish.

Get an HDI quote or a stackup review

HDIStackup.com does not build boards itself. Quotes, stack drawings and DFM reviews come from our manufacturing partner, PCBSync.

WhatsApp

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For quick questions: which build to use, whether a pitch is feasible, a rough price. Send the BGA part number and layer count and we will come back with a suggestion.

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Quote with files

For a firm price, send Gerbers or ODB++, drill files and the stack drawing through PCBSync's quote form. If the archive is too large for the form, send a download link on WhatsApp instead.

PCBSync includes a free DFM check with its quotes, so problems show up before you pay for anything.

Go to the PCBSync quote form

What to send

Gerber X2 or ODB++ for all layers, and one drill file per via span.
A stack drawing, or the build you want (for example 2+4+2) and the board thickness.
Impedance targets and the layers they apply to.
Via fill: which microvias stack, which vias sit in pads.
Laminate, surface finish, IPC class, quantity and delivery date.

What happens next

An engineer reviews the data or the question and replies on WhatsApp.
For a new design, you get a proposed stack drawing with dielectric thicknesses and impedance widths.
After a DFM check you get the quote, with lead time and any notes on the design.

About this page

Written by PCB design and fabrication engineers and run together with PCBSync, a PCB manufacturer in China. Quote requests from this page go to PCBSync, and the WhatsApp number reaches the same team.

Where the numbers come from

Definitions follow IPC-2226 (HDI design), IPC-6012 (qualification and performance), IPC-4761 (via fill), IPC-T-50 (terms) and IPC-TM-650 (test methods). Fabrication values are typical of current HDI shops. Your fabricator's stack drawing always takes priority.

The drawings

Every cross-section here is drawn from scratch: copper in orange, build-up in blue-green, core in beige, prepreg in pale green. You may use any figure in a review, course or article with credit and a link to hdistackup.com.